| 摘要 |
PURPOSE:To detect the abnormality of a system including a stop of clock pulses by adding a stop detecting circuit for clock pulses which are counted by a watch dog timer. CONSTITUTION:A CPU1 outputs clock pulses 31 on the basis of the oscillation frequency of a crystal oscillator 2. The clock pulses 31 are inputted to the watch dog timer 3 and clock stop detecting circuit 4. The clock stop detecting circuit 4 detects a stop of clock pulses 31 and outputs a clock stop error signal 33. When a watch dog timer reset signal 32 is stopped, a watchdog error detection signal 34 is outputted and other error signals 35 of a parity check error, etc., are gated by an OR gate 5 to generate an error signal 36. The error signal 36 is ORed with a reset signal 35 to generate a CPU reset signal 38. |
