| 摘要 |
PURPOSE:To attain an amplifying action with an operational amplifier for wide frequency band over the entire cycle of a clock signal, by applying the optimum gate bias voltage alternately to the gates of an output amplifying stage by means of two pairs of capacitors. CONSTITUTION:In the 1st differential circuit, the input voltage impressed to a reverse input terminal N11 is sent to the gate of a transistor (TR) Q11 via a capacitor C3 as well as to the gate of a TRQ14 via a capacitor C4 while a clock signal phi1 is kept on. Then the input voltage is amplified and delivered through a terminal N19. While the input voltage impressed to the terminal N11 is sent to the gate of the TRQ11 via a capacitor C1 and also to the gate of the TRQ14 via a capacitor C2 at the 1st differential circuit while a clock signal phi2 is kept on. The input voltage is amplified and delivered through a terminal N19. Thus a clock signal can be amplified over its entire cycle. |
