| 摘要 |
PURPOSE:To realize a complete software simulation by ICE by sending out different evaluation data to a bus in response to bus access based upon an optional status containing the same address of a CPU. CONSTITUTION:Set condition 52 is inputted to a condition holding memory 4 and evaluation data is inputted to a data holding memory 6 externally. Then, the program of a user system 1 begins to be executed. The CPU 2 accesses memories, etc. At this time, the address status 51 of the CPU 2 is sent out to a comparator 5 through a buffer 9. The comparator 5 compares the set condition 52 with the address status 51 to check whether they are coincident or not. When they are coincident, a bus 3 is connected to the side of the user system 1. When not, the bus 3 is switched by a switch 8 to the side of the data holding memory 6. When the CPU 2 finishes reading the evaluation data, a sequence counter 7 counts up by one with the trailing edge of a strobe pulse 71. Consequently, the address 61 of the data holding member 6 is updated for next evaluation data. |
