| 摘要 |
PURPOSE:To obtain directly original data with simple circuit constitution by gating a mudulation signal whose phase is controlled in response to a data difference signal for a prescribed period at adjacent data transmission periods and integrating the gated result. CONSTITUTION:A modulation signal (DPSK signal) whose phase is controlled in response to a data difference signal is gated for a prescribed period at a gate circuit 12. The timing of the gate is decided by a timing circuit 16 in response to a horizontal synchronizing signal. After the DPSK signal gated by the gate circuit 12 is integrated at an integration device 13, the result is fed to a comparator 18 via a peak hold circuit 17. The comparator 18 compares an output of the integration device 13 before one bit data transmission period held in the hold circuit 17 with an output of the integration device 13 at present and the DPSK signal is demodulated. |
