| 摘要 |
PURPOSE:To make it possible to easily perform constant speed control from a low speed to a high speed, by performing the judgement of a speed by using a T-trigger flip-flop reversed at every arrival of a speed signal to be judged, a counter and a memory circuit. CONSTITUTION:A T-trigger flip flop 14 is reversed at every arrival of a speed signal to be judged from a defferentiator 13. A counter 17 counts the reference clock from a reference clock oscillator 12 and set by the logical product conjunction of the speed signal to be judged and the output of the flip-flop 14. A D-flip-flop 18 stores carry outputted by the counter 17. An AND gate 19 outputs a delay time corresponding to the time of a speed slower than an objective speed and a NAND gate 20 outputs an advance time corresponding to the time of a speed faster than the objective speed. |
