| 摘要 |
PURPOSE:To eliminate a hardware amount by means of plural 0-order group channel time division multiplex processings by converting a 0-order group signal into a universal signal, applying time division processing and generating a time division multiplex processing type frame synchronizing signal. CONSTITUTION:n-Set of 0-order group channel data D0-Dn are given to memories 3-1-1-n, where they are written by a 64Kbit clock CLK and read as a universal signal by a clock CLK having the same speed as the multiplex speed generated by a timing generating circuit TG3-7, selected (3-2) and subject to selective multiplex sequentially in the unit of 8 signals in the 1/8 speed of the multiplexing speed of the TG3-7. The data is subject to S-P conversion 3-5, expanded into a 8-bit parallel signal by using the timing clock generated at a TG3-7, given to a memory 3-4, where it is written according to a frame address generated by an X-50 frame synchronism circuit 3-6 and read by an address generated by the TG3-7. The output of the memory 3-4 is subject to P-S conversion in the multiplexing speed of the TG3-7. |
