| 摘要 |
PURPOSE:To reduce the scale of a comparator circuit for difference absolute value by discriminating the sign bits of two subtractors at a time, by forwarding or reversing the inputs of the 1st and 2nd forward/reverse circuits for each bit according to the result of said discrimination of both sign bits. CONSTITUTION:The n-bit binary digital values (a-d) undergo the subtraction through subtractors 1a and 1b, and the offset binary values e=a-b and f=c-d are outputted. While the carry outputs (g) and (h) of the MSB of subtractors 1a and 1b are equal to '1' when the values (e) and (f) are positive and equal to '0' when the (e) and (f) are negative respectively. The signals (g) and (h) are sent to a control circuit 8. The circuit 8 obtains the positive or negative values (e) and (f) according to the same or different codes of signals (e) and (f). Then the combination output (r) of the values (e) and (f) is obtained by a full adder 7. Furthermore the circuit 8 controls a 1-bit multiplexer 9 by the control signal (v), and the output (s) of the multiplexer 9 is obtained from the result of comparison between the difference absolute value between values (a) and (b) and that between values (c) and (d). |
