发明名称 PRIORITY PROCESSING SYSTEM FOR INTER-PROCESSOR DATA TRANSFER
摘要 PURPOSE:To attain the dynamic change of priority for data transmission by reading a flag set on a main memory through a communication controller in an execution mode of a search queue command and controlling the counting action of a timer according to the contents of the flag. CONSTITUTION:Plural channel devices, e.g., block multiplexer channels BMC are connected under a processor, and communication controllers DEV-S and DEV-R are connected under the channels BMC. A means is provided to set flags OPEN and DTIM on a main memory MSU when the software of the processor replaces an enqueue pointer. Both flags OPEN and DTIM are read when the controller DEV-S executes a search queue command and set to flag registers 220 and 221 respectively. A timer control part 23 is started by the set contents for control the counting action of a timer 21. Then the timer when the device end is sent back is changed for execution of the dynamic change of priority for data transmission. Thus it is possible to cope with a data transfer request given from the processor.
申请公布号 JPS61214050(A) 申请公布日期 1986.09.22
申请号 JP19850057413 申请日期 1985.03.20
申请人 FUJITSU LTD 发明人 OWAKI TAKASHI
分类号 G06F15/16;G06F13/12;G06F13/38;G06F15/177 主分类号 G06F15/16
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