| 摘要 |
PURPOSE:To reduce a response waiting time of an input/output instruction, and to improve the throughput of a data processing device by reading out preferentially response data of the input/output instruction from a buffer. CONSTITUTION:An I/O response identifying circuit 6 identifies whether data sent from an adaptor is that to an I/O instruction or that of a cycle steal. When the I/O instruction response identifying circuit 6 detects response data of an I/O instruction, a value of a write address register 7 is set to a write address holding register 9. When a data transfer to a data processing device 3 from a buffer 4 becomes possible, a value of a readout address register 10 is shifted to a readout address holding register 12, and thereafter, the contents of the write address holding register 9 are shifted to the readout address register 10, and data of a corresponding buffer unit is read out. |
