| 摘要 |
PURPOSE:To provide many taps without decreasing the system efficiency by providing a shift register for at least one clock delay for the addition between units constituting a transversal filter. CONSTITUTION:Shift registers (SR) 401, 403, a data selector (DS)402 and a chip counter 404 are added newly so as to improve the addition of partial sum. A 1- clock delay 1-bit SR403 is inserted between input and output between units of a partial adder 205. Thus, the clock at partial sum is constant independently of the unit number L. The counter 404 consists of, e.g., a parallel adder 501 and a value more than the input data in a m-bit by 1 is outputted to an output terminal COUT. Thus, (i) is outputted in a binary number in m-bit at a counter output at the i-th chip. The DS402 receives it, the SR401 selects a data shifted by the i- stage among L sets of input data and the result is given to a terminal A of the adder 205. Thus, the data subjected to 1-clock shift is fed to an ADD.A terminal in the unit 1 and synchronized with the input ADD.B from the pre-stage. |
