| 摘要 |
PURPOSE:To eliminate the sampling noise mixed into an output with no reduction of the highest drive frequency and to improve the S/N ratio, by setting a prescribed output period of the stable signal for each bit of each train before the charge transfer outputs of two series are synthesized. CONSTITUTION:When a reset transistor TR1 is turned on with a signal phiR1, the stored carrier of an electrode 22' of a register A of a charge transfer device is supplied via an output gate 21. Then the voltage of a layer 2 is changed into the signal voltage. A stable output period TH1 during which the next phiR1 is impressed after a carrier is implanted to the layer 2 is set longer than a signal output period. So is with a register B. The output periods of both registers overlap with each other, and the outputs of both systems are synthesized via a TR5' and a TR15' to which pulses phiT1 and phiT2 are impressed respectively. No holding period is produced owing to the TR5' and TR15'. Furthermore one of both TRs is always kept on, and the impedance is reduced at a node 44. Thus the sampling noise produced when a pulse phi2 is changed to a low level can be eliminated. Then the S/N ratio is improved with no reduction of a drive frequency. |
