发明名称 PRIORITY DEGREE CONTROL SYSTEM OF BUS
摘要 PURPOSE:To reduce rise and fall of a use priority degree of each channel by constituting so that as for a bus controller, a DMA bus obtaining request of a channel always outputs a use permission, and as for each channel, an obtaining request signal is not sent out when it is in a use state. CONSTITUTION:When a channel 3 outputs a DMA bus obtaining request signal 100, a DMA bus controller 1 outputs a DMA bus use permitting signal 200. The channel 3 receives the DMA bus use permitting signal 200, and starts to use a DMA bus. A flip-flop 16 in the channel 3 is set, a DMA bus obtaining request flip-flop 14 is reset, and the channel 3 stops an output of the DMA bus obtaining request signal 100. The use permitting signal is always outputted onto the DMA bus from the DMA bus controller 1, but when it is seen from the channel, it is obtained by a signal having a trigger, therefore, only one channel which can use the DMA bus in the next time can be determined.
申请公布号 JPS6095672(A) 申请公布日期 1985.05.29
申请号 JP19830202580 申请日期 1983.10.31
申请人 TOSHIBA KK 发明人 IGARASHI SATORU
分类号 G06F13/37;G06F13/30 主分类号 G06F13/37
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