| 摘要 |
PURPOSE:To fetch an instruction at a high speed by comparing an output of a register for latching a low address from a CPU by fall of an RAS signal, with a low address sent out in the next time from the CPU. CONSTITUTION:A low address sent out of a CPU is latched to a register 2 by fall of an RAS signal. An output of this register 2 and a low address sent out in the next time from the CPU are compared by a comparator 3, and a coincidence signal is supplied to an RAS/CAS control part 4. This RAS/CAS control part 4 supplies only a CAS signal to a control storage part 1 by a coincidence output of the comparator 3, and instructs access by a page mode. Also, when an output of the comparator shows dissidence, the RAS signal is raised once, and the next instruction is fetched. |
