Apparatus for controlling writing of data into a memory having different read and write times

摘要

An apparatus for controlling the writing of data from a processor into a memory having different read and write times, wherein the memory is connected directly to the processor through address and data buses without the use of an input/output port. A timer circuit is connected to the buses and memory and is controlled by the processor to produce a write timing signal which controls the writing of data into the memory. The processor is placed in a holding state, based on the write timing signal, for a period long enough to assure that the data will be written into the memory in its entirety.