| 摘要 |
PURPOSE:To produce a MIS transistor with high withstand voltage assuring normal performance regardless of a pattern layout by a method wherein an extension of a gate electrode separating a source region from a drain region is arranged between itself and metallic wiring layer through the intermediary of an insulating film. CONSTITUTION:The ends of gate electrodes 26a and 26b are extended so that they may traverse a drain wiring 33 impressed with high voltage separated from interlayer insulating film 29 under the drain wiring 33. Through these procedures, an inverse layer may not be formed on an n type substrate 21 under the extention (ext) of the gate electrodes 26a, 26b since the (ext) are limited to the lower potential of the gate electrodes 26a, 26b. Therefore any leak current between source regions 27a, 27b and a drain region 28 may be prevented from flowing out since the inverse layer 34 formed on the substrate under the drain wiring 33 i.e. a channel cut region 22 is cut off at Gu under (ext) of the gate electrodes 26a, 26b. |
