| 摘要 |
PURPOSE:To calculate an accumulating circuit and to reduce the number of output bits by limiting the upper and lower limits of the output values of the accumulation to the value necessary for a servo system. CONSTITUTION:A speed counter 3 outputs a speed error signal (c) between the period of a speed detecting pulse (a) and the speed reference value, and an adder 4 outputs an encoded signal (d) produced by adding the signal (c) and the encoded signal (e) latched by a latch pulse (b) before one period by a latch circuit 5. The signal (d) is inputted to the latch circuit 5, and latched at the rising edge of the latch pulse (b). An adder 6 adds the added result (e) before one period and a new speed error signal (c), and applies it to a drive circuit 8. An upper and lower limit detector 10 limits the output of the latch circuit 5 when the result of the adder 4 exceeds the upper limit value and decreases lower than the lower limit. |
