发明名称 HIGH SPEED LOGICAL CIRCUIT
摘要 PURPOSE:To decrease the switching noise and also to handle a pulse having a high frequency by providing a capacitor in parallel with a feedback route at a part of a feedback section so as to reduce the impedence of the feedback circuit and reduce the response time. CONSTITUTION:An emitter of an inverse input transistor (TR) Q2 is connected to an emitter of input TRs Q1A, Q1B and Q1C and activated so as to be driven by the common emitter. A static capacitor C1 is connected between a base of the TRQ2 and a connecting point of load resistors RCO1, RCO2 of the Q2. When a current is switched while the inverse input TR is driven from the emitter, a dividing point of the RCO1, RCO2 being one connecting point of the static capacitor C1 does not respond to at first and its potential is not fluctuated. Thus, the base connecting point of the inverse input TRQ2 is decreased for the impedance by the electrostatic capacitor C1 and the switching noise is hardly superimposed. As a result, the propagation delay time of the circuit is decreased less than the case with absence of the capacitor C1.
申请公布号 JPS6091721(A) 申请公布日期 1985.05.23
申请号 JP19830198993 申请日期 1983.10.26
申请人 HITACHI SEISAKUSHO KK 发明人 YAGIYUU MASAYOSHI;ITOU HIROYUKI;MASAKI AKIRA
分类号 H03K19/082;H03K19/013;H03K19/086 主分类号 H03K19/082
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