| 摘要 |
PURPOSE:To decrease the processing time by allowing the processing to convert a transmitted character signal into a data in the unit of information to execute almost by using the hardware. CONSTITUTION:A data for one packet's share of the transmitted character signal is written in a 272-stage of shift register 24 in a form of serial data. The stored data of the register 24 is read serially in the unit of information and converted (25) into a parallel data. Then decoders 17, 18 and D.FF 14, 15 form the 1st pulse having the width from the start of count of a counter 16 to eight counts of clock pulses CP and the 2nd pulse having the width of six counts. When a packet control code PC is read from the register 24, the 1st pulse is selected and when a data other than the packet control code PC is read, the 2nd pulse is selected. A gate of an AND circuit 27 is opened with the selected pulse and the clock pulse CP is fed to shift registers 24, 25 as a shift clock. Thus, read work or the like is not required and the processing time is decreased. |
