| 摘要 |
PURPOSE:To prevent malfunction to an input change shorter than a set delay time by holding a counter output with a flip-flop and also resetting a counter with said output and an external input in a digital delay circuit. CONSTITUTION:When an input 9 is given, a counter 13 is operated and after the count of 8 clocks, an output 14 is set and becomes an input to a flip-flop 15 and a delay output 16 is set. When the delay output is set, a signal 12 is interrupted and the counter 3 is reset. When an input signal shorter than the delay time is inputted, since the polarity of input is changed before the delay output is changed, the counter 13 is reset and the state is restored to the initial state and malfunction is prevented. |
