| 摘要 |
<p>A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors (Ql, Q2) having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of each of the transistors, control the transfer of data bits from one row of such memory cells to another.</p> |
