发明名称 PARITY CHECK SYSTEM
摘要 PURPOSE:To simplify the correction of a control program by providing the information in response to data to decide whether a parity check should be carried out when the data is delivered. CONSTITUTION:ROMs R1 and R2 can store N words with one word defined as 8 bits respectively, and the control data are produced for each word. The ROMR2 contains parity bits B1-BN equivalent to a bit and enable bits E1-EN in response to each word. The control data stored in the ROMR1 is sent to a procesfor M as well as to a parity checker P. The parity information on bits B1-BN which are read out of the ROMR2 are sent to the checker P. While the enable information given from bits E1-EN are applied to an AND circuit A via an inverter I. The output of the checker P is supplied to the processor M via the circuit A.
申请公布号 JPS6091466(A) 申请公布日期 1985.05.22
申请号 JP19830198630 申请日期 1983.10.24
申请人 FUJITSU KK 发明人 SEKINE KOUICHI
分类号 G06F9/22;G06F11/10;G06F11/28;G06F12/16 主分类号 G06F9/22
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