发明名称 ADDRESS CONTROLLER OF MEMORY
摘要 PURPOSE:To read assuredly the program of an object to be controlled by adding selectively the address offset quantities corresponding to plural programs to the address signal given from a CPU and producting an address signal to a memory. CONSTITUTION:An address signal SI sent from CPU2 undergoes the address conversion through an address converting circuit 3 constituted as an external circuit to a microcomputer. Then an address signal S3 to be given to a memory 1 is applied to the memory 1 through an address bus 4. The circuit 3 receives the signal S1 transmitted from the CPU2 through an adder circuit 11 and adds it to an address offset signal S2. This addition output is sent to the bus 4 as an address signal S3.
申请公布号 JPS6091460(A) 申请公布日期 1985.05.22
申请号 JP19830197917 申请日期 1983.10.22
申请人 SONY KK 发明人 GOTOU HIDEAKI
分类号 G06F12/02;G06F12/06 主分类号 G06F12/02
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