| 摘要 |
PURPOSE:To expand a data address space with a simple constitution by using the control signal which is produced in response to execution of a definition instruction train of a CPU to an access control signal of an extended address memory. CONSTITUTION:An instruction multiplexer 11 connects logically an instruction input to an instruction output in a period while a CPU is executing a defined instruction. An address multiplexer 17 connects logically an address input to an address output. While a timing generating circuit 14 inactivates an extension instruction execution informing signal. When the CPU fetches an undefined instruction, i.e., an extension instruction, a defined instruction train in an instruction ROM18 is delivered. An extension instruction code is latched by an instruction register 12 and decoded by an instruction decoder 13. Based on the result of this decoding, a desired timing signal is produced by the circuit 14. |
