| 摘要 |
A common mode detector (10) for producing an output voltage (VA+VB)/2 in response to input voltages VA and VB contains a pair of MOS transistors (MA and MB) connected in series between a pair of input terminals A and B to which the input voltages (VA and VB) are to be applied. A separate feedback path runs from each input terminal (A, B) through a separate load device (LA2, LB2) to a gate control terminal of the respective MOS transistor (MA, MB), and a separate other feedback path runs from each input terminal (A, B) through a separate other load device (LA3, LB3) to a substrate terminal (SA, SB) of the respective MOS transistors. In this way, the respective feedback paths deliver to the respective gate terminals respective voltages equal to (VDD+VA)/2 and (VDD+VB)/2, respectively, while the other feedback paths deliver to the substrates of the respective MOS transistors (MA, MB) respective substrate bias voltages equal to (VSS+VA)/2 and (VSS+VB)/2, whereby the common mode voltage (VA+VB)/2 is developed at a node (AB) between the pair of MOS transistors (MA, MB).
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