| 摘要 |
PURPOSE:To detect surely wrong reading by providing a circuit which sets initial data having wrong parity to an RAM and an RAM for parity bit memory at a power-on time. CONSTITUTION:A wrong parity generating circuit 20 writes wrong parity bit data in all memory spaces of an RAM12 and an RAM14 for parity bit memory just after power is supplied to a computer body 1. A memory parity generating circuit 13 writes parity of write data in the RAM14 only when a CPU10 writes data in the RAM12. A memory parity check circuit 15 compares the parity value of read data with the parity value written by the circuit 13 only when the CPU 10 reads out data in the RAM12. If parity values coincide with each other as the comparison result, the CPU10 is instructed to continue processings; but if they do not coincide, an abnormality signal 15a is activated, and the CPU10 is instructed to interrupt processings. Thus, wrong reading is detected surely. |
