发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To eliminate a latch-up action generated by a parasitic transistor by a method wherein the second diffusion is provided in the first diffusion region located adjoining to the junction isolation region on the circumference of a bipolar element part, and the second diffusion region is circuit-connected to the bipolar element. CONSTITUTION:A transistor 10 consists of an N type epitaxial layer 18, a P type base region 19, an N<+> type region 15 and a P type region 21 to be used for isolation. A low resistor consists of the N<+> type region 15 located in a P type junction isolation region 22 and a P type region 20 to be used for isolation. Said transistor 10 and the low resistor are circuit-connected by a wiring layer 23. Accordingly, as the region 22 reaches a P<+> type substrate 24, the region 22 can be set at the earth potential through the substrate 24, and a non-conductive state is maintained at all times. Accordingly, the disturbance of circuit operation of the transistor 10 can be prevented by the parasitic transistor which is composed of the region 22, the layer 18 and the region 19.
申请公布号 JPS6086857(A) 申请公布日期 1985.05.16
申请号 JP19830195687 申请日期 1983.10.19
申请人 MATSUSHITA DENSHI KOGYO KK 发明人 OOTA MITSUHARU;YOSHIDA ISAO
分类号 H01L27/04;H01L21/331;H01L21/822;H01L21/8222;H01L27/06;H01L29/73;H01L29/732 主分类号 H01L27/04
代理机构 代理人
主权项
地址