| 摘要 |
<p>Data processing system architecture in which a central processing unit CPU (1) and a plurality of input/output processors I/OP (5-1, ... 5-N) said I/OP being connected in parallel through a BUS (6) can have access to a common working memory (4), under control of a memory access control unit (2), through a set of tridirectional gates (3) directly connecting memory (4) to the CPU (1) or to BUS (6) without interposition of registers, drivers, receivers, except said tridirectional gates, between internal CPU channel and memory channel.</p><p>Control unit (2) periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, missing such requests, CPU may activate memory cycles in synchronism with its internal cycles without preamble dialogue and access waiting time. If I/OP memory access requests are pending, control unit grants access to one I/OP on priority basis, activates a memory cycle and monitors in time relation with the memory cycle if other I/OP memory access requests are pending, further granting memory access without delay at the end of the memory cycle.</p><p>Missing further I/O memory access requests, control unit (2) resynchronizes its memory access request monitoring with the CPU internal cycles.</p> |
