| 摘要 |
<p>A digital code detector circuit for detecting on a priority basis those code combinations of an n-bit binary digital code (n>3) which contain only a single bit of one binary value (e.g. the code combinations 1000, 0100, 0010 and 0001 of a 4-bit binary digital code). The circuit comprises a set of n input leads with associated inverters to supply inverse code combinations as well as true input code combinations to a logic gating arrangement. The gating arrangement drives m output circuits, where the m is the number of bits of an output address code used to give an output address code for each possible input code combination of n-bits. When more than one of the input code combinations are present concurrently on the set of input leads, the gating arrangement is such that the m-bit address code for the input code combination having the higher (or highest) binary value is produced by the output circuits. Figure 3 shows one implementation of the detector circuit.</p> |
