Vector processing unit.

摘要

A functional unit (20) designed with arithmetic pipelining for vector processing is attached to a base data processor (22) from which it receives vector instructions and operands for processing. Stepping (53, 54) of operands and exception indicators through the vector processing unit is controlled (51) by the base processor (22, 52). Exception information (44) transferred (45) to the base processor is controlled to provide precise indicators (46) of error conditions for recovery and restart of vector processing. Masking logic (91-93) provides for expansion/contraction of operands in the vector processing unit (20) as compared with sequential main memory (21) addresses.