发明名称 |
Method and apparatus for controlling plurality of memory planes. |
摘要 |
<p>A method for controlling memory planes in a writing operation in a display control apparatus of a graphic system, the method including the steps of selectively connecting a plurality of memory planes (2-0,...2-3) to a data bus (DATA BUS) by an interface unit (4-0,...4-3f: selectively applying a write enable signal (WE) to the memory planes from a plane designating unit (3-0,...3-31; applying data to be written to the data bus from a central processing unit (CPU); writing the data into the memory planes to which the write enable signal has been applied and which are connected to the data bus; and writing predetermined fixed data into the memory planes to which is the write enable signal has been applied but which are not connected to the data bus.</p> |
申请公布号 |
EP0141521(A2) |
申请公布日期 |
1985.05.15 |
申请号 |
EP19840306458 |
申请日期 |
1984.09.21 |
申请人 |
FUJITSU LIMITED |
发明人 |
TAKAHASHI, HITOSHI;FUJISAKU, KIMINORI |
分类号 |
G06T1/00;G09G5/00;G09G5/02;G09G5/39;G09G5/393;G09G5/395;(IPC1-7):G09G1/16;G09G1/28 |
主分类号 |
G06T1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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