| 摘要 |
<p>A process, is disclosed for forming self aligned metal gate CMOS devices with guard rings isolating the active devices from each other and comprising only three mask steps prior to the contact mask where etching is done to contact junctions. The process is specifically defined for use with two layers of metal; the first metal layer provides source and drain contacts and spans the gate, the second metal layer providing device intraconnections. The three masking steps that are provided are a P well mask for defining the region in which N type devices are to be defined; a mask for defining the N type devices and guard rings; and a boron mask for defining the devices of the opposite type. (The sequence may, of course, be used to first define an N well, followed by diffusion of P type and then N type devices.) By the use of this sequence of masks, the active devices may be accurately placed, the gates are self aligned and by the use in combination therewith of low temperature controlled processing, very fine channel lengths are achieved. Further, the major surface of the device is very flat having no large steps either in the field areas between the devices or in the areas of the active devices.</p> |
