| 摘要 |
PURPOSE:To reduce a size of a MISFET and to enable high integration and high speed by determining the size of MISFET not to be a size which is required by an output stage of a logic circuit, but a size required by operation in the logic circuit. CONSTITUTION:N-channel MISFETs Qn1 and Qn2 are composed of gate electrodes 8 and semiconductor regions 9 and one of the semiconductor regions 9 which each of the MISFETs comprises is owned jointly. These are connected directly and compose ranks of n-channel MISFETs. Similarly, p-channel MISFETs Qp1 and Qp2 are composed of gate electrodes 8 and semiconductor regions 10 and these compose ranks of p-channel MISFETs. In basic cells 4A and 4B, two ranks of n-channel MISFETs and of p-channel MISFETs are arranged respectively. In order to compose CMISs easily, n-channel MISFETs arrays and p-channel MISFETs arrays are arranged in a direction of the same line with being adjacent to one another. |
