发明名称 PRIORITY PROCESSING SYSTEM OF INFORMATION TRANSFER CONTROL
摘要 PURPOSE:To eliminate the need to giving priority levels to all of input/output devices, and reduce the amount of circuit by setting only the number corresponding to a specific input/output device among plural input/output devices in a priority register. CONSTITUTION:A clock is normally supplied to the priority register 29, whose contents are updated. If a request for registering the number of the specific input device in a stack is made while the stack is full, the stack request is permitted only when a registration request having the number set in the priority register 29 or a higher priority number is made; and the permission of stack registration requests from other input/output devices are inhibited.
申请公布号 JPS6084655(A) 申请公布日期 1985.05.14
申请号 JP19830175627 申请日期 1983.09.21
申请人 FUJITSU KK;PANA FACOM KK 发明人 WADA OSAMU;KATAKURA OSAMU;HAIDA HIROTOSHI;ICHIJIYOU AKIHIRO
分类号 G06F13/36;G06F13/12;G06F13/14;G06F13/362 主分类号 G06F13/36
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