| 摘要 |
PURPOSE:To decrease a circuit scale while maintaining high speed capability by rearranging (N=mXn)-bit data in every (n) groups (m) bits unit at every time, and in every group in bit unit. CONSTITUTION:Latches 1-4 fetch 16-bit input data by every four bits at every time and a data rearranging circuit 5 rearranges data of four bits inputted from the latches 1-4 through a common bus 10. Latches 6-9, on the other hand, fetch the 4-bit data from the data rearranging circuit 6 through a common bus 11. Then, the data rearranging circuit 5 rearranges 4-bit data x1-x4 in four ways with control signals S0 and S1. |
