| 摘要 |
In the frequency control mode, a switch is ON. A power difference is fed back to an adder through a limiter and is compared with an output from a power setter. A difference signal from the adder is supplied to an adder to obtain a difference with detected power. By the feedback loop, the preset power is set to be substantially equal to the detected power. While the difference is greater than a predetermined value, an output from a level detector is at logic level "0". Even if a mode switch instruction is received in this state, an AND gate does not produce an output signal and the mode changing is not performed.
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