发明名称 VIDEO SIGNAL PROCESSING CIRCUIT
摘要 <p>A delay circuit comprising a pair of modulators for executing biaxial quadrature modulation with carriers that have a 90.degree. phase difference therebetween, a signal mixer which mixes the modulated output signals of the modulators together to produce a composite output signal, delay circuitry for delaying the composite output signal of the signal mixer and a pair of demodulators which are respectively associated with the pair of modulators and serve to demodulate the delayed output signal supplied by the delay circuitry. The first of the two demodulators associated with the first of the two modulators, produces a first demodulated output signal, a portion of which is supplied to the second of the two modulators as a modulating signal. Additionally, the first demodulated output signal is delayed by the delay circuitry for a predetermined duration with respect to an input signal fed to the first modulator. The second demodulator associated with the second modulator produces a second demodulated output signal which is delayed for twice the predetermined duration of the first modulator input signal.</p>
申请公布号 CA1187167(A) 申请公布日期 1985.05.14
申请号 CA19820406675 申请日期 1982.07.06
申请人 SONY CORPORATION 发明人 TANAKA, SADAAKI
分类号 H04N5/208;(IPC1-7):H04N9/04 主分类号 H04N5/208
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