| 摘要 |
PURPOSE:To enable the prevention of the latch-up breakdown of a CMOSIC and the like by a method wherein a power source voltage is supplied to said IC and the like via switching element. CONSTITUTION:When latch-up generates in an outside MOS integrated circuit IC1, a large current flows between the VDD terminal of the IC1 and the GND terminal, and the potential of the VDD terminal, i.e., the I/O terminal of a CPU comes close to a GND level (high level). A voltage detection circuit DC1 detects this voltage variation and outputs a signal at ''1'' level or ''0'' level to a control circuit. The control circuit CC1 stores the output signal of the DC1 and keeps a switching MOSFET1 at the OFF state for a constant time (e.g. 1mSec or more). Meantime, the relation of potentials in the IC1 the CMOSIC returns normal, and then this device can recover from the state of latch-up. The control circuit CC1 resets an FETT1 to the ON state after a constant time. |
