发明名称 WATCH DOG TIMER OF COMPUTER
摘要 PURPOSE:To attain size reduction and precision improvement by charging a capacitor through a transisitor (TR) which turns on and off at a specific period and discharging the capacitor with a clear signal, and generating a reset signal when the capacitor charge attains to a specific amount. CONSTITUTION:A clock signal phi and the clear signal CL generated by a specific instruction of a microcomputer are inputted to N channel enhancement MOS TRs 1 and 2 at the specific period, and the capacitor is charged when the signal phi is on and discharged with the signal CL; when its accumulated charge attains to the specific amount, the system reset signal RS is generated by an inverter 1 having large input impedance. Consequently, the number of elements is decreased to simplify the circuit constitution.
申请公布号 JPS6084644(A) 申请公布日期 1985.05.14
申请号 JP19830192732 申请日期 1983.10.15
申请人 MITSUBISHI DENKI KK 发明人 HAMANO HISANORI
分类号 G06F11/30;G06F11/00 主分类号 G06F11/30
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