Method for constructing delay circuits in a master slice IC

摘要

A method for constructing delay circuits in a master slice IC formed on a semiconductor substrate. The master slice IC comprises regularly arranged MIS transistors having gate electrodes. The MIS transistors includes various logic circuits. A delay circuit is formed between two logic circuits. The delay circuit comprises a resistor and a capacitor. The resistor is constructed using the resistances of the gate electrodes by sequentially connecting the gate electrodes between two logic circuits. The capacitor is constructed using capacitances formed between the gate electrodes and the semiconductor substrate. A precise delay time of a delay circuit having a small area can be obtained.