发明名称 DIGITAL TIME CONSTANT CIRCUIT
摘要 PURPOSE:To reduce the scale of hardware because only one multiplier by obtain a signal with a specific time constant for an input signal through a device consisting of a subtracter, scaling circuit, subtracter, multiplier, adder, and delay circuit. CONSTITUTION:An input step signal line 101 is connected to the positive-side input terminal (a) of a subtracter 11, whose output signal line 111 is connected to the input terminal (b) of the scaling circuit 12; and the output signal line 121 of the circuit 12 is connected to the input terminal (c) of a multiplier 13, whose output signal line 131 is connected to an input terminal (d) of an adder 14. The output signal 141 of this adder 14 is connected to the input terminal (e) of a one-sample delay device 15, whose output signal line 151 is connected to the minus-side input terminal (f) of a subtracter 11 and an input terminal (g) of the adder 14, thereby obtaining the signal with the specific time constant for the input step signal of the output signal line 141 of an adder 17.
申请公布号 JPS6081917(A) 申请公布日期 1985.05.10
申请号 JP19830190516 申请日期 1983.10.12
申请人 NIPPON DENKI KK 发明人 MORIMURA HIROSHI
分类号 H03H17/04;(IPC1-7):H03H17/04 主分类号 H03H17/04
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