| 摘要 |
<p>A circuit for controlling external bipolar buffers for an MOS peripheral device capable of operating in master and slave modes. The circuit provides for a slave mode logic block (40A) and a master mode logic (40B) block for generating a DATA TRANSMIT ENABLE SIGNAL to permit the bipolar buffer (17) to transmit data signals from the peripheral device (21) to a system bus (14, 15). The circuit also provides for a second slave mode logic block (60A) and a master mode logic block (60B) for generating a DATA RECEIVE ENABLE block to permit the bipolar buffer (17) to transmit data signals from the system bus (14, 15) to the peripheral device (21). Each slave mode logic block is responsive to condition signals, such as CHIP SELECT and READ/WRITE. Each master mode logic block is responsive to timing signals and signals generated internally within the peripheral device (21) so that the master mode DATA RECEIVE and DATA TRANSMIT signals occur only in predetermined timing cycles.</p> |
