| 摘要 |
PURPOSE:To attain data transfer in any case by allowing a slave chip to complete processing faster than a master chip without fail and to be turned to waiting status, and when data are transferred from the master chip, allowing the slave chip to release the waiting status and execute the succeeding processing. CONSTITUTION:At the time of data transfer, the slave chip is turned to a receivable state ealier than a master chip. In the slave chip, a transfer instruction TRAMS is generated from a control circuit and the output of an OR gate 42 is turned to an L level, so hat the contents of latches 71 are not changed. When a signal US is outputted from an AND gate 49 of the heat chip and applied to the slave chip, the output of the gate 42 is turned to an H level and the succeeding timing signal is generated from a clock generator. Consequently, a writing pulse WRITE is applied to a latch 54, transferred data are written and the contents of the written data are used by a control circuit in the succeeding program. |
