| 摘要 |
PURPOSE:To form a control electrode of low resistance having excellent thermal resistance by patterning a metal having ion stopping capacity on a W metal layer, sidewisely etching the W metal layer, and ion implanting for a main electrode region with the metal layer as a mask. CONSTITUTION:An n type active layer 2 is formed on a GaAs semi-insulating substrate 1, and a W metal layer 7 of low resistance and high thermal resistance is formed by a CVD method. A metal layer 8 for patterning Ni, Tr having ion implantation stopping capacity is formed, the layer 7 is etched, and the width of a gate electrode 9 is formed smaller in width than the layer 8 of the upside by sidewisely etching the layer 7. With the layer 8 and the electrode 9 as masks doner ions are implanted, and an n<+> type layer is formed as source and drain electrode region. The layer 8 is etched and removed to pattern the source and drain electrodes 10. The creep of the n<+> type layer to the portion directly under the gate can be stopped, and the rectifying contacting characteristics of the gate and the substrate can be stabilized. |
