发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To process efficiently an instruction and to improve the efficiency of processing by specifying plural branched addresses after decoding the instruction in accordance with the contents specified by a microinstruction register. CONSTITUTION:The reading of a machine word is specified by a microinstruction and data read out from a main storage device are stored in an instruction register IR1. The machine word instruction stored in the IR1 is decoded by a decoder 2, embeded in the place other than the lower two bits of a microprogram counter MPC3 and branched to a new microinstruction execution routine. A microinstruction register EMB4 forms the branching conditions of a decoded operation code so that plural branched addresses after the decoding of the operation code can be optionally set up from the conditions such as instruction types and the existence of the preceeding control. Consequently, one instruction in a control storage device 5 is read out to the EMB4 and executed in accordance with the address set up in the MPC3, so that the efficiency of the instruction processing is improved.
申请公布号 JPS6081646(A) 申请公布日期 1985.05.09
申请号 JP19830188382 申请日期 1983.10.11
申请人 HITACHI SEISAKUSHO KK 发明人 NAKAI KOUICHI;YUU KEIICHI;TSUNEHIRO TAKASHI;NAKAKOSHI JIYUNJI;HORI KEIJIROU
分类号 G06F9/22;G06F9/26;G06F9/28;G06F9/38 主分类号 G06F9/22
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