发明名称 |
Fault-tolerant memory array. |
摘要 |
<p>An array of memory cells (10-16) is organized as bytes of at least one bit in lenght, these memory cells being configured to conduct substantial current while in one of two states and not conduct substantial current while in the other of said two states and the arrangement being such that memory cells which fail when in operation do not conduct substantial current. The array is rendered fault-tolerant by the use of an address means (26) which simultaneously selects at least two of said bytes of memory cells and a sensing means which is connected to corresponding ones of the memory cells in the selected bytes of memory cells so as to the presence or absence of current flow in the corresponding ones of said memory cells. </p> |
申请公布号 |
EP0140698(A2) |
申请公布日期 |
1985.05.08 |
申请号 |
EP19840307427 |
申请日期 |
1984.10.29 |
申请人 |
SEEQ TECHNOLOGY INCORPORATED |
发明人 |
PERLEGOS, GEORGE |
分类号 |
G11C11/413;G06F11/18;G11C16/06;G11C17/00;G11C29/00;G11C29/04 |
主分类号 |
G11C11/413 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|