| 摘要 |
PURPOSE:To make refresh of a dynamic RAM possible without degrading the throughput of a system by not using CPUs or the like but using a private external logic circuit. CONSTITUTION:An FF2 outputs a hold request signal (HRQ) by a pulse of a refresh timer 1. When a hold request acknowledge signal (HLDA) becomes high- level, the HLDA signal triggers an FF3 and an address counter 6 to open gates 7 and 8 and connects the output of a counter 6 and the output of a shift register (SR) 4 to an address bus and a control bus respectively. In the first stage of the SR 4, a pulse having a pulse width corresponding to one clock period is sent for the purpose of clearing the FF3. A false memory read signal (MRD) is sent by outputting outputs in the second and the third stages of the SR 4 synchronously with the fall of a clock by an FF5. After this sending, the output in the fourth stage of the SR 4 clears the FF2 to release the hole request. |
