| 摘要 |
PURPOSE:To secure the operation of an error detecting circuit invariably during normal operation by providing an error detection part which checks input data consisting of plural bits and a latch part whose output is inverted in every prescribed cycle. CONSTITUTION:When the register 1 consisting of 8-bit data bits a0-a9 and one parity bit ap is detected by a parity checker 2, the output of a D type latch 6 as a copy of the output of a T type latch 5 connected to the EOR circuit 7 for the parity bit ap is supplied to an EOR circuit 8 together with the output of the checker 2. Then when the output of the latch 5 is ''0'', the circuit 7 outputs the value of the parity a7 as it is, so such a trouble that an error is detected although the data in the register 1 and an input to the checker 2 are correct is detected; when the output of the latch 5 is ''1'', the value of the parity ap is inverted, so such a trouble that no error is detected although the data in the register 1 is correct and the input to the checker 2 is wrong is detected during the operation. |
