| 摘要 |
PURPOSE:To operate a memory accurately without narrowing the pulse width of a write control signal even if the device is operated in a high speed, by providing a pulse generating circuit which detects the rise or the fall of the write control signal to generate an internal write pulse having a prescribed pulse width. CONSTITUTION:A write control signal WE having a pulse width Tw is inputted to an input buffer Gi, and an internal signal phiw having the in-phase as this signal WE and an internal signal phiw having the opposite phase are generated. The internal signal having the opposite phase is delayed by a delay circuit D to obtain a signal phiwd, and this signal is supplied to an OR circuit Go together with the signal phiw. As the result, an internal write pulse WE' which is determined by a delay time (d) of the circuit D and has a pulse width shorter than that of the control signal WE is generated by the OR circuit Go and is supplied to a read/write circuit. Consequently, since the write control signal WE is converted to the narrow-width write pulse WE' internally even if the write control signal WE having a wide pulse width is given from the external, malfunction is prevented even if the trailing edge of the external write control signal WE comes to the next cycle. |
