| 摘要 |
PURPOSE:To use an inexpensive and low power consumption type memory elements and speed up writing and reading operation by writing and reading data at a rate obtained by dividing a memory cycle time into N equally. CONSTITUTION:A memory access address 8 and write data 9 are distributed to and written in two memory units 20A and 20B on the arrival of every clock signal 22 with timing signals 10A and 10B generated alternately by a control circuit 21. When reading operation is performed, the control circuit 21 outputs read gate signals 13A and 13B corresponding to the timing signals 10A and 10B with a W/R switching signal 11 to control the memory units 20A and 20B, outputting an output address 16 and output data 17. Consequently, inexpensive and low power consumption type elements are used to double the W/R speed. In this case, when N sets of memory units are used, the speed become N-fold. |
