| 摘要 |
PURPOSE:To quicken the switching speed of a MOS FET by connecting a series circuit comprising the 1st and 2nd capacitors between a positive and a negative terminal of a DC power supply and connecting a common line to a common connecting point between the 1st and 2nd capacitors so as to obtain a positive/ negative dual power supply. CONSTITUTION:Bases of an NPN transistor (TR) 14 and a PNP TR 15 are connected in common, the common connecting point is connected to a collector of a TR 7, emitters are connected also in common and its common connecting point is connected to a gate G of the MOS FET 17 via a resistor 16. In turning the FET 17 from ON to OFF state, a terminal voltage 2Ed/3 of a capacitor 5 is used to apply a reverse bias to a charging voltage Ed/3 of a capacitor C0 between the gate G and source S of the FET 17, and in turning the FET 17 from OFF to ON state, a terminal voltage 2Ed/3 of a capacitor 4 is used to apply forward bias to a charge voltage -Ed/3 of the capacitor C0 between the gate G and source S of the FET 17. |
